Routability Prediction for Field Programmable Gate Arrays with a Routing Hierarchy

The author has granted a non-exclusive licence allowing the National Library of Canada to reproduce, loan, distn'bute or seil copies of this thesis in microfonn, paper or electronic formats. The author retains ownership of the copyright in this thesis. Neither the thesis nor substantial extracts from it may be printed or otherwise reproduced without the author's permission. L'auteur a accordé une licence non exclusive permettant à la Bibliothèque nationale du Canada de reproduire, prêter, distribuer ou vendre des copies de cette thèse sous la forme de microfiche/fh, de reproduction sur papier ou sur format électronique. L'auteur conserve la propriété du droit d'auteur qui protège cette thèse. Ni la thèse ni des extraits substantiels de celle-ci ne doivent être imprimés ou autrement reproduits sans son autorisation. Field Programmable Gate Arrays (FPGAs) have emerged in the last fifteen years as a key technology for implernenting digital circuits in VLSI. Much research has been done on their architecture and applications. One particularly important area of study is routing implementation, which is greatly affected by the routing architecture and routing resources. This thesis explores the effective utiIization of a routing hierarchy that can be present in conventional FPGAs as well as in hienrchical FPGAs (HFPGAs). A statistical model is adopted to investigate the routability on both kinds of FPGAs. The performance of our proposed FPGA models is compared to those without a routing hierarchy. Experimental methods are used to determine the flexibility and switch consumption of various routing resources. Results show that integrating a routing resource hierarchy into FPGAs consumes fewer routing resources and that the speed of designs implemented in the FPGAs can be greatly improved.